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a adm1030 * information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. rev. a intelligent temperature monitor and pwm fan controller functional block diagram serial bus interface interrupt status register va l u e a n d li mit registers offset registers configuration register limit comparator 2.5v b andgap reference analog multiplexer b andgap temperature sensor slave address register add sda scl gnd adm1030 fa n characteristics register f an speed config register t min /t range register fa n speed counter address pointer register pwm controller ta ch signal conditioning nc int therm fan_fault nc nc nc pwm_out ta ch/ain d+ d v cc adc nc = no connect features op ti mized for pentium iii: all ows reduced guar dbanding so ft war e and automatic fan speed control automatic fan speed control allows control independent of cpu intervention after initial setup control loop minimizes acoustic noise and battery consumption remote temperature measurement accurate to 1 c using remote diode 0.125 c resolution on remote temperature channel local temperature sensor with 0.25 c resolution pulsewidth modulation fan control (pwm) programmable pwm frequency programmable pwm duty cycle tach fan speed measurement analog input to measure fan speed of 2-wire fans (using sense resistor) 2-wire system management bus (smbus) with ara support overtemperature therm output pin programmable int output pin configurable offset for all temperature channels 3 v to 5.5 v supply range shutdown mode to minimize power consumption applications no tebook pcs, network servers and personal computers telecommunications equipment product description the adm1030 is an acpi-compliant two-channel digital ther- mometer and under/over temperature alarm, for use in compu ters and thermal management systems. optimized for the pentium iii, the higher 1 c accuracy offered allows sys tems designers to sa fely reduce temperature guardbanding and increase system performance. a pulsewidth modulated (pwm) fan control out- put controls the speed of a cooling fan by varying output duty c ycle. duty cycle values between 33%?00% allow smooth control of the fan. the speed of the fan can be monitored via a tach input for a fan with a tach output. the tach input can be programmed as an analog input, allowing the speed of a 2-wire f an to be determined via a sense resistor. the device will also detect a stalled fan. a dedicated fan speed control loop pro- vides control even without the intervention of cpu software. it also ensures that if the cpu or system locks up, the fan can s till be controlled based on temperature measurements, and the fan speed adjusted to correct any changes in system tem perat ure. fan speed may also be controlled using existing acpi software. o ne input (two pins) is dedicated to a remote t emperature- sensing diode with an accuracy of 1 c, and a local temperature sensor allows ambient temperat ure to be monitored. the device has a programmable int output to indicate error conditions. t here is a dedicated fan_fault output to sig nal fan failure. the therm pin is a fail-safe output for over -temperature conditions that can be used to throttle a cpu clock. * patents pending.
rev. a ? adm1030?pecifications 1 (t a = t min to t max , v cc = v min to v max , unless otherwise noted.) parameter min typ max unit test conditions/comments power supply supply voltage, v cc 3.0 3.30 5.5 v supply current, i cc 1.4 3 ma interface inactive, adc active 32 50 m a standby mode temperature-to-digital converter internal sensor accuracy 1 3 c resolution 0.25 c external diode sensor accuracy 1 c60 c t d 100 c resolution 0.125 c remote sensor source current 180 m a high level 11 m a low level open-drain digital outputs ( therm , int , fan_fault , pwm_out) output low voltage, v ol 0.4 v i out = ?.0 ma; v cc = 3 v high-level output leakage current, i oh 0.1 1 m av out = v cc ; v cc = 3 v digital input leakage current input high current, i ih ? m av in = v cc input low current, i il 1 m av in = 0 input capacitance, c in 5pf digital input logic levels 2 (add, therm , tach) input high voltage, v ih 2.1 v input low voltage, v il 0.8 v open-drain serial data bus output (sda) output low voltage, v ol 0.4 v i out = ?.0 ma; v cc = 3 v high-level output leakage current, i oh 0.1 1 m av out = v cc serial bus digital inputs (scl, sda) input high voltage, v ih 2.1 v input low voltage, v il 0.8 v hysteresis 500 mv fan rpm-to-digital converter accuracy 6% 60 c t a 100 c resolution 8 bits tach nominal input rpm 4400 rpm divisor n = 1, fan count = 153 2200 rpm divisor n = 2, fan count = 153 1100 rpm divisor n = 4, fan count = 153 550 rpm divisor n = 8, fan count = 153 conversion cycle time 637 ms serial bus timing 3 clock frequency, f sclk 10 100 khz see figure 1 glitch immunity, t sw 50 ns see figure 1 bus free time, t buf 4.7 m s see figure 1 start setup time, t su;sta 4.7 m s see figure 1 start hold time, t hd;sta 4 m s see figure 1 stop condition setup time t su;sto 4 m s see figure 1 scl low time, t low 1.3 m s see figure 1 scl high time, t high 450 m s see figure 1 scl, sda rise time, t r 1000 ns see figure 1 scl, sda fall time, t f 300 ns see figure 1 data setup time, t su;dat 250 ns see figure 1 data hold time, t hd;dat 300 ns see figure 1 notes 1 typicals are at t a = 25 c and represent most likely parametric norm. shutdown current typ is measured with v cc = 3.3 v. 2 add is a three-state input that may be pulled high, low or left open-circuit. 3 timing specifications are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.2 v for a rising edge. specifications subject to change without notice.
rev. a adm1030 ? absolute maximum ratings * positive supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . 6.5 v voltage on any input or output pin . . . . . . . . ?.3 v to +6.5 v input current at any pin . . . . . . . . . . . . . . . . . . . . . . . 5 ma package input current . . . . . . . . . . . . . . . . . . . . . . . 20 ma maximum junction temperature (t jmax ) . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature, soldering vapor phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared 15 sec . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 c esd rating all pins . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 v * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics 16-lead qsop package q ja = 105 c/w, q jc = 39 c/w ordering guide temperature package package model range description option adm1030arq 0 c to 100 c 16-lead qsop rq-16 t su:sto p s p t hd:sta t su:sta t su:dat t high t f t hd:dat t r t low t hd:sta t buf s scl sda figure 1. diagram for serial bus timing caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adm1030 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. a adm1030 ? pin function descriptions pin no. mnemonic description 1 pwm_out digital output (open-drain). pulsewidth modulated output to control fan speed. requires pull-up resistor (10 k w typical). 2 tach/ain digital/analog input. fan tachometer input to measure fan speed. may be reprogrammed as an analog input to measure speed of a 2-wire fan via a sense resistor (2 w typical) 3, 4, 11, 12 nc not connected. 5 gnd system ground. 6v cc p ower. can be powered by 3.3 v standby power if m onitoring in low power states is required. 7 therm digital i/o (open-drain). an active low thermal overload output that indicates a violation of a temperature set point (overtemperature). also acts as an input to provide external fan control. when this pin is pulled low by an external signal, a status bit is set, and the fan speed is set to full-on. requires pull-up resistor (10 k w ). 8 fan_fault digital output (open-drain). can be used to signal a fan failure. requires pull-up resistor (typically 10 k w ). 9d analog input. connected to cathode of an external temperature-sensing diode. the tempera ture- sensing element is either a pentium iii substrate transistor or a general-purpose 2n3904. 10 d+ analog input. connected to anode of the external temperature-sensing diode. 13 add three-state logic input. sets two lower bits of device smbus address. 14 int digital output (open-drain). can be programmed as an interrupt output for temperature/fan speed interrupts. requires pull-up resistor (10 k w typical). 15 sda digital i/o. serial bus bidirectional data. open-drain output. requires pull-up resistor (2.2 k w typical). 16 scl digital input. serial bus clock. requires pull-up resistor (2.2 k w typ). pin configuration top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 pwm_out scl adm1030 ta ch/ain sda nc int nc add gnd nc v cc nc therm d+ fan_fault d nc = no connect
rev. a ? t ypical performance characteristicsadm1030 leakage resistance ?m 15 10 1 100 3.3 remote temperature error ? c 10 30 ? ?0 5 0 ?0 ?5 dxp to gnd dxp to v cc (3.3v) tpc 1. temperature error vs. pcb track resistance frequency ?hz 17 0 remote temperature error ? c 15 13 11 9 7 5 3 1 ? 500k 2m 4m 6m 10m 100m 400m v in = 100mv p-p v in = 200mv p-p tpc 2. temperature error vs. power supply noise frequency frequency ?hz ? 0 400m 100k 1m 100m 200m 300m 2 0 3 1 500m remote temperature error ? c 7 6 5 4 v in = 40mv p-p v in = 20mv p-p tpc 3. temperature error vs. common-mode noise frequency piii temperature ? c 80 0 060 10 reading ? c 20 30 40 50 70 60 50 30 10 40 20 70 80 90 100 110 90 110 100 tpc 4. pentium iii temperature measurement vs. adm1030 reading dxp ?dxn capacitance ?nf ? ?0 147 2.2 remote temperature error ? c 3.3 4.7 10 22 ? ? ? ? ? 1 ?1 ?2 ?3 ?4 ?5 ?6 0 ? ? ? tpc 5. temperature error vs. capacitance between d+ and d sclk frequency ?khz 80 0 0 75 1 supply current ? a 5 10 25 50 70 60 50 30 10 40 20 100 250 500 750 1000 90 100 110 v cc = 5v v cc = 3.3v tpc 6. standby current vs. clock frequency
rev. a adm1030 ? tpc 7. temperature error vs. differential-mode noise frequency tpc 8. standby supply current vs. supply voltage tpc 9. local sensor error tpc 10. remote sensor error tpc 11. supply current vs. supply voltage frequency ?hz 7 ? 0 400m 100k remote temperature error ? c 1m 100m 200m 300m 6 5 4 2 0 3 1 500m v in = 30mv p-p v in = 20mv p-p supply voltage ?v 200 supply current ? a 180 160 140 60 120 80 40 20 0 100 ?0 0 1.1 1.3 1.5 1.7 1.9 2.1 2.5 2.9 4.5 add = hi-z add = gnd add = v cc temperature ? c 0.08 0 error ? c 0 ?.08 ?.16 ?.24 ?.32 ?.40 ?.48 ?.56 ?.64 ?.72 ?.80 20 40 60 80 85 100 105 120 supply voltage ?v 1.30 0.80 2.0 supply current ?ma 2.4 1.25 1.20 1.15 1.05 0.95 1.10 1.00 0.90 0.85 2.8 3.2 3.6 4.0 4.4 4.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 time ?sec 120 20 0 temperature ? c 2 110 100 90 70 50 80 60 40 30 46810 13579 10 0 tpc 12. response to thermal shock temperature ? c 0.16 0 error ? c 0.08 0 ?.08 ?.16 ?.24 ?.32 ?.40 ?.48 ?.56 ?.64 ?.72 ?.80 ?.88 20 40 60 80 85 100 105 120
rev. a adm1030 ? general description the adm1030 is a temperature monitor and pwm fan control- ler for microprocessor-based systems. the device communicates with the system via a serial system management bus. the serial bus controller has a hardwired address pin for device selection (pin 13), a serial data line for reading and writing addresses and data (pin 15), and an input line for the serial clock (pin 16). all c ontrol and programming functions of the adm1030 are per- formed over the serial bus. the device also supports the smbus alert response address (ara) function. internal registers of the adm1030 a brief description of the adm1030? principal internal regis- ters is given below. more detailed information on the function of each register is given in table xii to table xxvi. configuration register p rovides control and configuration of various functions on the device. address pointer register this register contains the address that selects one of the other internal registers. when writing to the adm1030, the first byte of data is always a register address, which is written to the ad dress pointer register. status registers these registers provide status of each limit comparison. value and limit registers t he results of temperature and fan speed measurements are stored in these registers, along with their limit values. fan speed config register this register is used to program the pwm duty cycle for the fan. offset registers allows the temperature channel readings to be offset by a 5-bit two? complement value written to these registers. these values will automatically be added to the temperature values (or sub- tracted from if negative). this allows the systems designer to optimize the system if required, by adding or subtracting up to 15 c from a temperature reading. fan characteristics register this register is used to select the spin-up time, pwm frequency, and speed range for the fan used. therm limit registers these registers contain the temperature values at which therm will be asserted. t min /t range registers these registers are read/write registers that hold the minimum temperature value below which the fan will not run when the device is in automatic fan speed control mode. these regis- ters also hold the values defining the range over that auto fan control will be provided, and hence determines the temperature at which the fan will run at full speed. serial bus interface c ontrol of the adm1030 is carried out via the smbus. the adm1030 is connected to this bus as a slave device, under the control of a master device, e.g., the 810 chipset. the adm1030 has a 7-bit serial bus address. when the device is powered up, it will do so with a default serial bus address. the five msbs of the address are set to 01011, the two lsbs are determined by the logical state of pin 13 (add). this is a three-state input that can be grounded, connected to v cc , or left open-circuit to give three different addresses. the state of the add pin is only sampled at power-up, so changing add with power on will have no effect until the device is powered off, then on again. table i. add pin truth table add pin a1 a0 gnd 0 0 no connect 1 0 v cc 01 if add is left open-circuit, the default address will be 0101110. the facility to make hardwired changes at the add pin allows the user to avoid conflicts with other devices sharing the same se rial bus, for example, if more than one adm1030 is used in a system. the serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line sda while the serial clock line scl remains high. t his indicates that an address/data stream will follow. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next 8 bits, consisting of a 7-bit address (msb first) plus an r/ w bit that determines the di rection of the data transfer, i.e., whether d ata will be written to or read from the slave device. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowl- edge bit. all other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is a 0, the master w ill write to the slave device. if the r/ w bit is a 1, the master will read from the slave device. 2. d ata is sent over the serial bus in sequen ces of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. when all data bytes have been read or written, stop condi- tions are established. in write mode, the master will pull the data line high during the tenth clock pulse to assert a stop condition. in read mode, the master device will override the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master will then take the data line low during the low period before the tenth clock p ulse, then high during the tenth clock pulse to assert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at t he beginning and cannot subsequently be changed without starting a new operation.
rev. a adm1030 ? in the case of the adm1030, write operations contain either one or two bytes, and read operations contain one byte, and perform the following functions. to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed; data can then be written into that register or read from it. the first byte of a write operation always contains an address that is stored in the address pointer regis ter. if data is to be written to the device, then the write operation contains a second data byte that is written to the register selected by the address pointer register. this is illustrated in figure 2a. the device address is sent over the bus followed by r/ w set to 0. this is followed by two data b ytes. the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register. when reading data from a register there are two possibilities: 1. if the adm1030? address pointer register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. this is done by performing a write to the adm1030 as before, but only the data byte containing the register address is sent, as data is not to be written to the register. this is shown in figure 2b. a read operation is then performed consisting of the serial bus address, r/ w bit set to 1, followed by the data byte read from the data register. this is shown in figure 2c. 2. if the address pointer register is known to be already at the d esired address, data can be read from the corresponding data register without first writing to the address pointer register, so figure 2b can be omitted. notes 1. although it is possible to read a data byte from a data register without first writing to the address pointer r egister, if the address pointer register is already at the correct value, it is not possible to write data to a register without writing to the a ddress pointer register, because the first data byte of a write is always written to the address pointer register. 2. in figures 2a to 2c, the serial bus address is shown as the default value 01011(a1)(a0), where a1 and a0 are set by the three-state add pin. 3. t he adm1030 also supports the read byte protocol, as described in the system management bus specification. r/w 0 scl sda 10 1 1 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a ck. by adm1030 start by master 19 1 a ck. by adm1030 9 d7 d6 d5 d4 d3 d2 d1 d0 a ck. by adm1030 stop by master 1 9 scl (continued) sda (continued) frame 1 serial bus address byte frame 2 address pointer register byte frame 3 data byte figure 2a. writing a register address to the address pointer register, then writing data to the selected register r/w 0 scl sda 10 1 1 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a ck. by adm1030 start by master 19 1 a ck. by adm1030 9 frame 1 serial bus address byte frame 2 address pointer register byte stop by master figure 2b. writing to the address pointer register only r/ w 0 scl sda 10 1 1 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 no ack. by master start by master 19 1 a ck. by adm1030 9 frame 1 serial bus address byte frame 2 da ta byte from adm1030 stop by master figure 2c. reading data from a previously selected register
rev. a adm1030 ? alert response address alert response address (ara) is a feature of smbus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. t he int output can be used as an interrupt output or can be used as an s mbalert . one or more int outputs can be connected to a common smbalert line connected to the master. if a device? int line goes low, the following procedure occurs: 1. smbalert pulled low. 2. m aster initiates a read operation and sends the alert re sponse address (ara = 0001 100). this is a general call address that must not be used as a specific device address. 3. the device whose int output is low responds to the alert response address, and the master reads its device address. the address of the device is now known and can be interro- gated in the usual way. 4. if more than one device? int output is low, the one with the lo west device address will have priority, in accordance with normal smbus arbitration. 5. o nce the adm1030 has responded to the alert response address, it will reset its int output; however, if the error condition that caused the interrupt persists, int will be reasserted on the next monitoring cycle. temperature measurement system internal temperature measurement the adm1030 contains an on-chip bandgap temperature sen- sor. the on-chip adc performs conversions on the output of this sensor and outputs the temperature data in 10-bit two? complement format. the resolution of the local temperature sensor is 0.25 c. the format of the temperature data is shown in table ii. external temperature measurement t he adm1030 can measure the temperature of an external diode sensor or diode-connected transistor, connected to pins 9 and 10. th ese pins are a dedicated temperature input channel. the function of pin 7 is as a therm input/output and is used to flag overtemperature conditions. the forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coeff icient of about ? mv/ c. unfortunately, the absolute v alue of v be , varies from device to device, and individual calibration is required to null this out, so the technique is u nsuitable for mass production. the technique used in the adm1030 is to measure the change in v be when the device is operated at two different currents. this is given by: d v be = kt/q ln ( n ) where: k is boltzmann? constant. q is charge on the carrier. t is absolute temperature in kelvins. n is ratio of the two currents. fi gure 3 shows the input signal conditioning used to measure the output of an external temperature sensor. this figure shows t he external sensor as a substrate transistor, provided for tempera- tu re monitoring on some microprocessors, but it could equally well be a discrete transistor. low-pass filter f c = 65khz bias diode remote sensing transistor in ii bias d+ d v out+ v out to adc v dd figure 3. signal conditioning if a discrete transis tor is used, the collector will not be grounded, and should be linked to the base. if a pnp transistor is used, the base is connected to the d?input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the d?input and the base to the d+ input. one lsb of the adc corresponds to 0.125 c, so the adm1030 can t heoretically measure temperatures from ?27 c to +127.75 c, although ?27 c is outside the operating range for the device. the extended temperature resolution data format is shown in tables iii and iv. table ii. temperature data format (local temperature and remote temperature high bytes) temperature ( c) digital output ?28 c 1000 0000 ?25 c 1000 0011 ?00 c 1001 1100 ?5 c 1011 0101 ?0 c 1100 1110 ?5 c 1110 0111 ? c 1111 1111 0 c 0000 0000 +1 c 0000 0001 +10 c 0000 1010 +25 c 0001 1001 +50 c 0011 0010 +75 c 0100 1011 +100 c 0110 0100 +125 c 0111 1101 +127 c 0111 1111
rev. a adm1030 ?0 table iii. remote sensor extended temperature resolution extended remote temperature resolution ( c) low bits 0.000 000 0.125 001 0.250 010 0.375 011 0.500 100 0.625 101 0.750 110 0.875 111 the extended temperature resolution for the local and remote channels is stored in the extended temperature resolution register (register 0x06), and is outlined in table xviii. table iv. local sensor extended temperature resolution extended local temperature resolution ( c) low bits 0.00 00 0.25 01 0.50 10 0.75 11 to prevent ground noise interfering with the measurement, the m ore negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the d?input. if the sensor is used in a very noisy environment, a capacitor of value up to 1000 pf may be placed between the d+ and d inputs to filter the noise. to measure d v be , the sensor is switched between operating currents of i and n i. the res ulting waveform is passed through a 65 khz low-pass filter to remove noise, then to a chopper- stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage pro- portional to d v be . this voltage is measured by the adc to give a temperature output in 11-bit two? complement format. to further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. an external temperature measurement nominally takes 9.6 ms. layout considerations digital boards can be electrically noisy environments and care must be taken to protect the analog inputs from noise, particu- la rly when measuring the very small voltages from a remote diode sensor. the following precautions should be taken: 1. place the adm1030 as close as possible to the remote sens- ing diode. provided that the worst noise sources such as clock generators, data/address buses, and crts are avoided, this distance can be 4 to 8 inches. 2. route the d+ and d?tracks close together, in parallel, with grounded guard tracks on each side. provide a ground plane under the tracks if possible. 3. use wide tracks to minimize inductance and reduce noise pick-up. 10 mil track minimum width and spacing is recommended. 10mil 10mil 10mil 10mil 10mil 10mil 10mil gnd d+ d gnd figure 4. arrangement of signal tracks 4. try to minimize the number of copper/solder joints, which can cause thermocouple effects. where copper/solder joints are used, make sure that they are in both the d+ and d path and at the same temperature. thermocouple effects should not be a major problem as 1 c corresponds to about 200 m v, and thermocouple voltages are a bout 3 m v/ c of temperature difference. unless there are two thermocouples with a big temperature differential between t hem, thermocouple voltages should be much less than 200 m v. 5. place a 0.1 m f bypass capacitor close to the adm1030. 6. if the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. this will work up to about 6 to 12 feet. 7. f or really long distances (up to 100 feet) use shielded twisted pair such as belden #8451 microphone cable. connect the twisted pair to d+ and d?and the shield to gnd close to the adm1030. leave the remote end of the shield uncon- nected to avoid ground loops. because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. when using long cables, the filter capacitor c1 may be reduced or removed. in any case the total shunt capaci- tance should not exceed 1000 pf. cable resistance can also introduce errors. 1 w series resistance introduces about 0.5 c error. addressing the device add (pin 13) is a three-state input. it is sampled, on power-up to set the lowest two bits of the serial bus address. up to three addresses are available to the systems designer via this address pin. this reduces the likelihood of conflicts with other devices attached to the system management bus. the adm1030 interrupt system the adm1030 has two interrupt outputs, int and therm . these have different functions. int responds to violations of so ftware programmed temperature limits and is maskable (de scribed in more detail later). therm is intended as a ?ail-safe?interrupt output that can- not be masked. if the temperature is below the low temperature limit, the int pin will be asserted low to indicate an out-of-limit c ondition. if the tem perature exceeds the high tem perature limit, the int pin will also be asserted low. a third limit; therm limit, may be programmed into the device to set the temperature lim it abo ve which the overtemperature therm p in will be
rev. a adm1030 ?1 asserted low. the behavior of the high limit and therm limit is as follows: 1. whenever the temperature measured exceeds the high tem- perature limit, the int pin is asserted low. 2. if the temperature exceeds the therm limit, the therm output asserts low. this can be used to throttle the cpu clock. if the therm -to-fan enable bit (bit 7 of therm behavior/revision register) is cleared to 0, the fan will not run full-speed. the therm limit may be programmed at a lower temperature than the high temperature limit. this allows the system to run in silent mode, where the cpu can be throttled while the cooling fan is off. if the temperature continues to increase, and exceeds the high temperature limit, an int is generated. software may then decide whether the fan should run to cool the cpu. this allows the system to run in silent mode. 3. if the therm -to-fan enable bit is set to 1, the fan will run full-speed whenever therm is asserted low. in this case, both throttling and active cooling take place. if the high temperature limit is programmed to a lower value than the therm limit, exceeding the high temperature limit will assert int low. software could change the speed of the fan depending on temperature readings. if the temperature con- tinues to increase and exceeds the therm limit, therm asserts low to throttle the cpu and the fan runs full-speed. this allows the system to run in performance mode, w here active cooling takes place and the cpu is only throttled at high temperature. using the high temperature limit and the therm limit in this way allows the user to gain maximum performance from the system by only slowing it down, should it be at a critical temperature. although the adm1030 does not have a dedicated interrupt mask register, clearing the appropriate enable bits in configu- ration register 2 will clear the appropriate interrupts and mask out future interrupts on that channel. disabling interrupt bits will prevent out-of-limit conditions from generating an interrupt or setting a bit in the status registers. using therm as an input the therm pin is an open-drain input/output pin. when used as an output, it signals over-temperature conditions. when asserted low as an output, the fan will be driven full-speed if the therm -to-fan enable bit is set to 1 (bit 7 of register 0x3f). when therm is pulled low as an input, the therm bit (bit 7) of status register 2 is set to 1, and the fan is driven full-speed. note that the therm -to-fan enable bit has no effect when- ever therm is used as an input. if therm is pulled low as an input, and the therm -to-fan enable bit = 0, the fan will still be driven full-speed. the therm -to-fan enable bit only affects the behavior of therm when used as an output. status registers all out-of-limit conditions are flagged by status bits in status registers 1 and 2 (0x02, 0x03). bits 0 and 1 (alarm speed, fan fault) of status register 1, once set, may be cleared by reading status register 1. once the alarm speed bit is cleared, this bit will not be reass erted on the next monitoring cycle even if the c ondition still persists. this bit may be reasserted only if the fan is no longer at alarm speed. bit 1 (fan fault) is set whenever a fan tach failure is detected. once cleared, it will reassert on subsequent fan tach failures. bits 2 and 3 of status register 1 are the remote temperature high and low status bits. exceeding the high or low temperature limits for the external channel sets these status bits. reading the status register clears these bits. however, these bits will be reasserted if the out-of limit condition still exists on the next monitoring cycle. bits 6 and 7 are the local temperature high and low status bits. these behave exactly the same as the remote temper- ature high and low status bits. bit 4 of status register 1 indicates that the remote temperature therm limit has been exceeded. this bit gets cleared on a read of status register 1 (see figure 5). bit 5 indicates a remote diode error. this bit will be a 1 if a short or open is detected on the remote temperature channel on power-up. if this bit is set to 1 on power-up, it cannot be cleared. bit 6 of status register 2 (0x03) indicates that the local therm limit has been exceeded. this bit is cleared on a read of status register 2. bit 7 indicates that therm has been pulled low as an input. this bit can also be cleared on a read of status register 2. 5 int rearmed status reg. read temp therm limit therm int figure 5. operation of therm and int signals fi gure 5 shows the interaction between int and therm . once a critical temperature therm limit is exceeded, both int and therm assert low. reading the status registers clears the interrupt and the int pin goes high. however, the therm pin remains asserted until the measured temperature falls 5 c below the exceeded therm limit. this feature can be used to cpu throttle or drive a fan full-speed for maximum cooling. note, that the int pin for that interrupt source is not r earmed until the temperature has fallen below the therm limit ? c. this prevents unnecessary interrupts from tying up valuable cpu resources. modes of operation the adm1030 has four different modes of operation. these modes determine the behavior of the system. 1. automatic fan speed control mode. 2. filtered automatic fan speed control mode. 3. pwm duty cycle select mode (directly sets fan speed under software control). 4. rpm feedback mode.
rev. a adm1030 ?2 automatic fan speed control the adm1030 has a local temperature channel and a remote temperature channel, which may be connected to an on-chip diode-connected transistor on a cpu. these two temperature channels may be used as the basis for an automatic fan speed c ontrol loop to drive a fan using pulsewidth modulation (pwm). how does the control loop work? the automatic fan speed control loop is shown in fig- ure 6 below. fa n speed max min temperature t min t max = t min + t range spin up for 2 seconds figure 6. automatic fan speed control in order for the fan speed control loop to work, certain loop parameters need to be programmed into the device. 1. t min . the temperature at which the fan should switch on and run at minimum speed. the fan will only turn on once the temperature being measured rises above the t min value programmed. the fan will spin up for a predetermined time (default = 2 secs). see fan spin-up section for more details. 2. t range . the temperature range over which the adm1030 will automatically adjust the fan speed. as the temperature increases beyond t min , the pwm_out duty cycle will be increased accordingly. the t range parameter actually defines the fan speed versus temperature slope of the control loop. 3. t max . the temperature at which the fan will be at its maxi- mum speed. at this temperature, the pwm duty cycle driving the fan will be 100%. t max is given by t min + t range . since this parameter is the sum of the t min and t range parameters, it does not need to be programmed into a register on-chip. 4. a hysteresis value of 5 c is included in the control loop to prevent the fan continuously switching on and off if the tem- perature is close to t min . the fan will continue to run until such time as the temperature drops 5 c below t min . figure 7 shows the different control slopes determined by the t range value chosen, and programmed into the adm1030. t min was set to 0 c to start all slopes from the same point. it can be seen how changing the t range value affects the pwm duty cycle versus temperature slope. temperature ? c pwm duty cycle ?% 0 100 93 87 80 73 66 60 53 47 40 33 t min t max = t min + t range 510 20 4 06080 t range = 80 c t range = 40 c t range = 20 c t range = 10 c t range = 5 c figure 7. pwm duty cycle vs. temperature slopes (t range ) figure 8 shows how, for a given t range , changing the t min value affects the loop. increasing the t min value will increase the t max (temperature at which the fan runs full speed) value, since t max = t min + t range . note, however, that the pwm duty cycle vs temperature slope remains exactly the same. changing the t min value merely shifts the control slope. the t min may be changed in increments of 4 c. temperature ? c pwm duty cycle ?% 0 100 93 87 80 73 66 60 53 47 40 33 t min t max = t min + t range 20 40 60 80 t range = 40 c t range = 40 c t range = 40 c figure 8. effect of increasing t min value on control loop fan spin-up as was previously mentioned, once the temperature being mea- sured exceeds the t min value programmed, the fan will turn on at minimum speed (default = 33% duty cycle). however, the problem with fans being driven by pwm is that 33% duty cycle is not enough to reliably start the fan spinning. the solution is to spin the fan up for a predetermined time, and once the fan has spun up, its running speed may be reduced in line with the temperature being measured. th e adm1030 allows fan spin-up times between 200 ms and 8 seconds. bits <2:0> of fan characteristics register 1 (register 0x20) program the fan spin-up time.
rev. a adm1030 ?3 table v. fan spin-up times spin-up time bits 2:0 (fan characteristics register 1) 000 200 ms 001 400 ms 010 600 ms 011 800 ms 100 1 sec 101 2 secs (default) 110 4 secs 111 8 secs once the automatic fan speed control loop parameters have been chosen, the adm1030 device may be programmed. the adm1030 is placed into automatic fan speed control mode by setting bit 7 of configuration register 1 (register 0x00). the device powers up into automatic fan speed control mode by default. the control mode offers further flexibility in that the user can decide which temperature channel/chan- nels control the fan. table vi. auto mode fan behavior bits 6, 5 control operation (config register 1) 00 remote temperature controls the fan. 11 maximum speed calculated by local and remote temperature channels control the fan. when bits 5 and 6 of config register 1 are both set to 1, it offers increased flexibility. the local and remote temperature channels can have independently programmed control loops with different control parameters. whichever control loop calculates the fastest fan speed based on the temperature being measured, drives the fan. figure 9 shows how the fan? pwm duty cycle is determined by two independent control loops. this is the type of auto mode fan behavior seen when bits 5 and 6 of config register 1 are set to 11. figure 9a shows the control loop for the local tem- perature channel. its t min value has been programmed to 20 c, and its t range value is 40 c. the local temperature? t max w ill thus be 60 c. figure 9b shows the control loop for the remote temperature channel. its t min value has been set to 0 c, while its t range = 80 c. therefore, the remote temperature? t max value will be 80 c. consider if both temperature channels measure 40 c. both control loops will calculate a pwm duty cycle of 66%. there- fore, the fan will be driven at 66% duty cycle. if both temperature channels measure 20 c, the local channel will calculate 33% pwm duty cycle, while the remote channel will calculate 50% pwm duty cycle. thus, the fan will be driven at 50% pwm duty cycle. consider the local temperature measuring 60 c while the remote temperature is measuring 70 c. the pwm duty cycle calculated by the local temperature control loop will be 100% (since the temperature = t max ). the pwm duty cycle calculated by the remote temperature control loop at 70 c will be approximately 90%. so the fan will run full-speed (100% duty cycle). remember, that the fan speed will be based on the fastest speed calculated, and is not necessarily based on the highest temperature measured. depending on the control loop parameters programmed, a lower temperature on one channel, may actually calculate a faster speed, than a higher temperature on the other channel. local temperature ? c pwm duty cycle ?% 0 100 93 87 80 73 66 60 53 47 40 33 t min t max = t min + t range 20 40 60 t range = 40 c a. remote temperature ? c pwm duty cycle ?% 0 100 93 87 80 73 66 60 53 47 40 33 t min t max = t min + t range 20 40 80 70 t range = 80 c b. figure 9. max speed calculated by local and remote temperature control loops drives fan programming the automatic fan speed control loop 1. program a value for t min . 2. program a value for the slope t range . 3. t max = t min + t range . 4. program a value for fan spin-up time. 5. program the desired automatic fan speed control mode behavior, i.e., which temperature channel controls the fan. 6. select automatic fan speed control mode by setting bit 7 of configuration register 1. other control loop parameters having programmed all the above loop parameters, are there any other parameters to worry about? t min was defined as being the temperature at which the fan sw itched on and ran at minimum speed. this minimum speed is 33% duty cycle by default. if the minimum pwm duty cycle is pro grammed to 33%, the fan control loops will operate as previously de scribed.
rev. a adm1030 ?4 it should be noted however, that changing the minimum pwm duty cycle affects the control loop behavior. s lope 1 of figure 10 shows t min set to 0 c and the t range chosen is 40 c. in this case, the fan? pwm duty cycle will vary over the range 33% to 100%. the fan will run full-speed at 40 c. if the minimum pwm duty cycle at which the fan runs at t min is changed, its effect can be seen on slopes 2 and 3. take case 2, where the minimum pwm duty cycle is reprogrammed from 33% (default) to 53%. temperature ? c 100 93 87 80 73 66 60 47 40 33 t min 16 28 40 60 0 pwm duty cycle ?% 53 t range = 40 c figure 10. effect of changing minimum duty cycle on control loop with fixed t min and t range values the fan will actually reach full-speed at a much lower tempera- ture, 28 c. case 3 shows that when the minimum pwm duty cycle was increased to 73%, the temperature at which the fan ran full-speed was 16 c. so the effect of increasing the mini- mum pwm duty cycle, with a fixed t min and fixed t range , is that the fan will actually reach full-speed (t max ) at a lower temperature than t min + t range . how can t max be calculated? in automatic fan speed control mode, the register that holds the minimum pwm duty cycle at t min , is the fan speed config register (register 0x22). table vii shows the relation- s hip between the decimal values written to the fan speed config register and pwm duty cycle obtained. table vii. programming pwm duty cycle decimal value pwm duty cycle 00 0% 01 7% 02 14% 03 20% 04 27% 05 33% (default) 06 40% 07 47% 08 53% 09 60% 10 (0x0a) 67% 11 (0x0b) 73% 12 (0x0c) 80% 13 (0x0d) 87% 14 (0x0e) 93% 15 (0x0f) 100% the temperature at which the fan will run full-speed (100% duty cycle) is given by: t max = t min + (( max dc ? min dc ) t range /10) where, t max =t emperature at which fan runs full-speed. t min =t emperature at which fan will turn on. max dc =m aximum duty cycle (100%) = 15 decimal. min dc =d uty cycle at t min , programmed into fan speed config register (default = 33% = 5 decimal). t range =p wm duty cycle versus temperature slope. example 1 t min =0 c, t range = 40 c min dc = 53% = 8 decimal (table vii) calculate t max . t max =t min + ((max dc ?min dc) t range /10) t max =0 + ((100% dc ?53% dc) 40/10) t max =0 + ((15 ?8) 4) = 28 t max = 28 c (as seen on slope 2 of figure 10) example 2 t min =0 c, t range = 40 c min dc = 73% = 11 decimal (table vii) calculate t max . t max =t min + ((max dc ?min dc) t range /10) t max =0 + ((100% dc ?73% dc) 40/10) t max =0 + ((15 ?11) 4) = 16 t max = 16 c (as seen on slope 3 of figure 10) example 3 t min =0 c, t range = 40 c min dc = 33% = 5 decimal (table vii) calculate t max . t max =t min + ((max dc ?min dc) t range /10) t max =0 + ((100% dc ?33% dc) 40/10) t max =0 + ((15 ?5) 4) = 40 t max = 40 c (as seen on slope 1 of figure 10) in this case, since the minimum duty cycle is the default 33%, the equation for t max reduces to: t max =t min + ((max dc ?min dc) t range /10) t max =t min + ((15 ?5) t range /10) t max =t min + (10 t range /10) t max = t min + t range
rev. a adm1030 ?5 relevant registers for automatic fan speed control mode register 0x00 configuration register 1 <7> logic 1 selects automatic fan speed control, logic 0 selects software control (default = 1). <6:5> 00 = remote temperature controls fan 11 = fa s test calculated speed controls the fan when bit 7 = logic 1. register 0x20 fan characteristics register 1 <2:0> fan 1 spin-up time 000 = 200 ms 001 = 400 ms 010 = 600 ms 011 = 800 ms 100 = 1 sec 101 = 2 secs (default) 110 = 4 secs 111 = 8 secs <5:3> pwm frequency driving the fan 000 = 11.7 hz 001 = 15.6 hz 010 = 23.4 hz 011 = 31.25 hz (default) 100 = 37.5 hz 101 = 46.9 hz 110 = 62.5 hz 111 = 93.5 hz <7:6> speed range n; defines the lowest fan speed that can be measured by the device. 00 = 1: lowest speed = 2647 rpm 01 = 2: lowest speed = 1324 rpm 10 = 4: lowest speed = 662 rpm 11 = 8: lowest speed = 331 rpm register 0x22 fan speed configuration register <3:0> min speed: this nibble contains the speed at which the fan will run when the temperature is at t min . the default is 0x05, meaning that the fan will run at 33% duty cycle when the temperature is at t min . register 0x24 local temp t min /t range <7:3> local temp t min . these bits set the temperature at which the fan will turn on when under auto fan speed control. t min can be programmed in 4 c increments. 00000 = 0 c 00001 = 4 c 00010 = 8 c 00011 = 12 c | | 01000 = 32 c (default) | | 11110 = 120 c 11111 = 124 c <2:0> local temperature t range . this nibble sets the tem- perature range over which automatic fan speed control takes place. 000 = 5 c 001 = 10 c 010 = 20 c 011 = 40 c 100 = 80 c register 0x25 remote temperature t min /t range <7:3> rem ote temperature t min . sets the temperature at which the fan will switch on based on remote tempera- ture readings. 00000 = 0 c 00001 = 4 c 00010 = 8 c 00011 = 12 c | | 01100 = 48 c | | 11110 = 120 c 11111 = 124 c <2:0> remote temperature t range . this nibble sets the tem- perature range over which the fan will be controlled based on remote temperature readings. 000 = 5 c 001 = 10 c 010 = 20 c 011 = 40 c 100 = 80 c
rev. a adm1030 ?6 filtered control mode the automatic fan speed control loop reacts instantaneously to changes in temperature, i. e., the pwm duty cycle will respond immediately to temperature change. in certain circumstances, we may not want the pwm output to react instantaneously to temperature changes. if significant variations in temperature were found in a system, it would have the effect of changing the fan speed, which could be obvious to someone in close proxim- ity. one way to improve the system? acoustics would be to slow down the loop so that the fan ramps slowly to its newly calcul ated fan speed. this also ensures that temperature transients will effectively be ignored, and the fan? operation will be smooth. there are two means by which to apply filtering to the auto- matic fan speed control loop. the first method is to ramp the fan speed at a predetermined rate, to its newly calculated value instead of jumping directly to the new fan speed. the second approach involves changing the on-chip adc sample rate, to change the number of temperature readings taken per second. the filtered mode on the adm1030 is invoked by setting bit 0 of the fan filter register (register 0x23). once the fan filter register has been written to, and all other control loop param- eters (t min , t range , etc.) have been programmed, the device may be placed into automatic fan speed control mode by setting bit 7 of configuration register 1 (register 0x00) to 1. effect of ramp rate on filtered mode bits <6:5> of the fan filter register determine the ramp rate in filtered mode. the pwm_out signal driving the fan will have a period, t, given by the pwm_out drive frequency, f, since t = 1/f. for a given pwm period, t, the pwm period is subdi- v ided into 240 equal time slots. one time slot corresponds to the smallest possible increment in pwm duty cycle. a pwm signal of 33% duty cycle will thus be high for 1/3 240 time slots and low for 2/3 240 time slots. therefore, 33% pwm duty cycle corresponds to a signal which is high for 80 time slots and low for 160 time slots. pwm_out 33% duty cycle 160 time slots 80 time slots pwm output (one period) = 240 time slots figure 11. 33% pwm duty cycle represented in time slots the ramp rates in filtered mode are selectable between 1, 2, 4, and 8. the ramp rates are actually discrete time slots. for example, if the ramp rate = 8, then eight time slots will be added to the pwm_out high duty cycle each time the pwm_out duty cycle needs to be increased. figure 12 shows how the filtered mode algorithm operates. increment previous pwm value by ramp rate read temperature calculate new pwm duty cycle is new pwm value > previous value? decrement previous pwm value by ramp rate yes no figure 12. filtered mode algorithm the filtered mode algorithm calculates a new pwm duty cycle based on the temperature measured. if the new pwm duty cycle value is greater than the previous pwm value, the previous pwm duty cycle value is incremented by either 1, 2, 4, or 8 time slots (depending on the setting of bits <6:5> of the fan filter regis- ter). if the new pwm duty cycle value is less than the previous pwm value, the previous pwm duty cycle is decremented by 1, 2, 4, or 8 time slots. each time the pwm duty cycle is incremented or decremented, it is stored as the previous pwm duty cycle for the next comparison. so what does an increase of 1, 2, 4, or 8 time slots actually mean in terms of pwm duty cycle? a ramp rate of 1 corresponds to one time slot, which is 1/240 of the pwm period. in filtered auto fan speed control mode, incrementing or decrementing by 1 changes the pwm output duty cycle by 0.416%. table viii. effect of ramp rates on pwm_out ramp rate pwm duty cycle change 1 0.416% 2 0.833% 4 1.66% 8 3.33% so programming a ramp rate of 1, 2, 4, or 8 simply increases or decreases the pwm duty cycle by the amounts shown in ta b le v, depending on whether the temperature is increasing or decreasing. figure 13 shows remote temperature plotted against pwm duty c ycle for filtered mode. the adc sample rate is the highest sample rate; 11.25 khz. the ramp rate is set to 8 which would correspond to the fastest ramp rate. with these settings it took a pproximately 12 seconds to go from 0% duty cycle to 100% duty cycle (full-speed). the t min value = 32 c and the t range = 80 c. it can be seen that even though the temperature increased very rapidly, the fan gradually ramps up to full speed.
rev. a adm1030 ?7 time ?s 012 140 80 40 60 20 0 80 60 40 20 0 120 120 100 pwm duty cycle ?% r temp ? c 100 r temp pwm duty cycle figure 13. filtered mode with ramp rate = 8 figure 14 shows how changing the ramp rate from 8 to 4 affects the control loop. the overall response of the fan is slower. since t he ramp rate is reduced, it takes longer for the fan to achieve full running speed. in this case, it took approximately 22 seconds for the fan to reach full speed. time ?s 022 120 80 40 60 20 0 140 80 60 40 20 0 110 120 100 pwm duty cycle ?% r temp ? c r temp pwm duty cycle figure 14. filtered mode with ramp rate = 4 figure 15 shows the pwm output response for a ramp rate of 2. in this instance the fan took about 54 seconds to reach full running speed. 80 60 40 20 0 120 100 r temp ? c time ?s 054 140 80 40 60 20 0 120 pwm duty cycle ?% 100 r temp pwm duty cycle figure 15. filtered mode with ramp rate = 2 finally, figure 16 shows how the control loop reacts to tem- perature with the slowest ramp rate. the ramp rate is set to 1, while all other control parameters remain the same. with the slowest ramp rate selected it took 112 seconds for the fan to reach full speed. time ?s 0 112 120 80 40 60 20 0 140 80 60 40 20 0 110 120 100 pwm duty cycle ?% r temp ? c r temp pwm duty cycle figure 16. filtered mode with ramp rate = 1 as can be seen from figures 13 through 16, the rate at which the fan will react to temperature change is dependent on the ramp rate selected in the fan filter register. the higher the r amp rate, the faster the fan will reach the newly calculated fan speed. figure 17 shows the behavior of the pwm output as tempera- ture varies. as the temperature is rising, the fan speed will ramp up. small drops in temperature will not affect the ramp-up func- tion sin ce the newly calculated fan speed will still be higher than the previous pwm value. the filtered mode allows the pwm output to be made less sensitive to temperature variations. this will be dependent on the ramp rate selected and the adc sample rate programmed into the fan filter register. 90 90 time ?s 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 00 pwm duty cycle ?% r temp ? c r temp pwm duty cycle figure 17. how fan reacts to temperature variation in filtered mode
rev. a adm1030 ?8 effect of adc sample rate on filtered mode the second means by which to change the filtered mode char- acteristics is to adjust the adc sample rate. the faster the adc s ample rate, the more temperature samples are obtained per second. one way to apply filtering to the control loop is to slow down the adc sampling rate. this means that the num- ber of iterations of the filtered mode algorithm per second are effectively reduced. if the number of temperature measure- ments per second are reduced, how often the pwm_out signal controlling the fan is updated is also reduced. bits <4:2> of the fan filter register (reg 0x23) set the adc sample rate. the default adc sample rate is 1.4 khz. the adc sample rate is selectable from 87.5 hz to 11.2 khz. table ix shows how m any temperature samples are obtained per second, for each of the adc sample rates. table ix. temperature updates per second adc sample rate temperature updates/sec 87.5 hz 0.0625 175 hz 0.125 350 hz 0.25 700 hz 0.5 1.4 khz 1 (default) 2.8 khz 2 5.6 khz 4 11.2 khz 8 relevant registers for filtered automatic fan speed control mode in addition to the registers used to program the normal auto- matic fan speed control mode, the following register needs to be programmed. register 0x23 fan filter register <7> spin-up disable :- when this bit is set to 1, fan spin-up is disabled. (default = 0) <6:5> ramp rate: these bits set the ramp rate for filtered mode. 00 = 1 (0.416% duty cycle change) 01 = 2 (0.833% duty cycle change) 10 = 4 (1.66% duty cycle change) 11 = 8 (3.33% duty cycle change) <4:2> adc sample rate 000 = 87.5 hz 001 = 175 hz 010 = 350 hz 011 = 700 hz 100 = 1.4 khz (default) 101 = 2.8 khz 110 = 5.6 khz 111 = 11.2 khz <1> unused. default = 0 <0> fan 1 filter enable: when this bit is set to 1, it enables filtering on fan 1. default = 0. programming the filtered automatic fan speed control loop 1. program a value for t min . 2. program a value for the slope t range . 3. t max = t min + t range . 4. program a value for fan spin-up time. 5. program the desired automatic fan speed control mode behavior, i.e., which temperature channel controls the fan. 6. program a ramp rate for the filtered mode. 7. program the adc sample rate in the fan filter register. 8. set bit 0 to enable fan filtered mode for the fan. 9. select automatic fan speed control mode by setting bit 7 of configuration register 1. pwm duty cycle select mode the adm1030 may be operated under software control by clear- ing bit 7 of configuration register 1 (register 0x00). this allows the user to directly control pwm duty cycle. clearing bit 5 of configuration register 1 allows fan control by varying pwm duty cycle. values of duty cycle between 0% to 100% may be written to the fan speed config register (0x22) to control the speed of the fan. table x shows the relationship between hex values written to the fan speed configuration register and pwm duty cycle obtained. table x. pwm duty cycle select mode hex value pwm duty cycle 00 0% 01 7% 02 14% 03 20% 04 27% 05 33% 06 40% 07 47% 08 53% 09 60% 0a 67% 0b 73% 0c 80% 0d 87% 0e 93% 0f 100%
rev. a adm1030 ?9 rpm feedback mode the second method of fan speed control under software is rpm feedback mode. this involves programming the desired fan rpm value to the device to set fan speed. the advantages include a very tightly maintained fan rpm over the fan? life, and virtu- ally no acoustic pollution due to fan speed variation. fans typically have manufacturing tolerances of 20%, meaning a wide variation in speed for a typical batch of identical fan models. if it is required that all fans run at exactly 5000 rpm, it may be necessary to specify fans with a nominal fan speed of 6250 rpm. how ever, many of these fans will run too fast and make excess noise. a fan with nominal speed of 6250 rpm could run as fast as 7000 rpm at 100% pwm duty cycle. rpm mode will allow all of these fans to be programmed to run at the desired rpm value. clearing bit 7 of configuration register 1 (reg 0x00) to 0 places the adm1030 under software control. once under soft- ware control, the device may be placed in to rpm feedback mode by writing to bit 5 of configuration register 1. writing a 1 to bit 5 selects rpm feedback mode for the fan. once rpm feedback mode has been selected, the required fan rpm may be written to the fan tach high limit register (0x10). the rpm feedback mode function allows a fan rpm value to be programmed into the device, and the adm1030 will maintain the selected rpm value by monitoring the fan tach and speed- ing up the fan as necessary, should the fan start to slow down. conversely, should the fan start to speed up due to aging, the rpm feedback will slow the fan down to maintain the correct rpm speed. the value to be programmed into each fan tach high limit register is given by: count = ( f 60)/ r n where: f = 11.25 khz r = desired rpm value n = speed range; must be set to 2 the speed range, n , really determines what the slowest fan speed measured can be before generating an interrupt. the slowest fan speed will be measured when the count value reaches 255. since speed range, n, = 2, count = ( f 60)/ r n r = ( f 60)/ count n r = (11250 60)/255 2 r = (675000)/510 r = 1324 rpm , fan fail detect speed. programming rpm values in rpm feedback mode rather than writing a value such as 5000 to a 16-bit register, an 8-bit count value is programmed instead. the count to be pro- grammed is given by: count = ( f 60)/ r n where: f = 11.25 khz r = desired rpm value n = speed range = 2 example 1: if the desired value for rpm feedback mode is 5000 rpm, what value needs to be programmed for count? count = ( f 60)/ r n since the desired rpm value, r , is 5000 rpm, the value for count is: n = 2: count = (11250 60)/5000 2 count = 675000/10000 count = 67 (assumes 2 tach pulses/rev). example 2: if the desired value for rpm feedback mode is 3650 rpm, what value needs to be programmed for count? count = ( f 60)/ r n since the desired rpm value, r , is 3650 rpm, the value for count is: n = 2: count = (11250 60)/3650 2 count = 675000/7300 count = 92 (assumes 2 tach pulses/rev). once the count value has been calculated, it should be written to the fan tach high limit register. it should be noted that in rpm feedback mode, there is no high limit register for under- speed detection that can be programmed as there are in the other fan speed control modes. the only time each fan will indicate a fan failure condition is whenever the count reaches 255. since the speed range n = 2, the fan will fail if its speed drops below 1324 rpm. programming rpm values 1. choose the rpm value to be programmed. 2. set speed range value, n = 2. 3. calculate count value based on rpm and speed range val- ues chosen. use count equation to calculate count value. 4. clear bit 7 of configuration register 1 (reg. 0x00) to place the adm1030 under software control. 5. write a 1 to bit 5 of configuration register 1 to place the device in rpm feedback mode. 6. write the calculated count value to the fan tach high limit register (reg. 0x10). the fan speed will now go to the desired rpm value and maintain that fan speed. rpm feedback mode limitations rpm feedback mode only controls fan rpm over a limited fan speed range of about 75% to 100%. however, this should be enough range to overcome fan manufacturing tolerance. in prac- tice, however, the program must not function at too low an rpm value for the fan to run at, or the rpm mode will not operate. to find the lowest rpm value allowed for a given fan, do the following:
rev. a adm1030 ?0 1. run the fan at 53% pwm duty cycle in software mode. clear bits 5 and 7 of configuration register 1 (reg 0x00) to enter pwm duty cycle mode. write 0x08 to t he fan speed config register (reg 0x22) to set the pwm output to 53% duty cycle. 2. measure the fan rpm. this represents the fan rpm below which the rpm mode will fail to operate. do not program a lower rpm than this value when using rpm feedback mode. 3. en sure that speed range, n, = 2 when using rpm feed- back mode. fans come in a variety of different options. one distinguishing feature of fans is the number of poles that a fan has internally. the most common fans available have four, six, or eight poles. the number of poles the fan has generally affects the number of pulses per revolution the fan outputs. if the adm1030 is used to drive fans other than 4-pole fans that output 2 tach pulses/revolution, then the fan speed measurement equation needs to be adjusted to calculate and display the cor- rect fan speed, and also to program the correct count value in rpm feedback mode. fan speed measurement equations for a 4-pole fan (2 tach pulses/rev): fan rpm = ( f 60)/ count n for a 6-pole fan (3 tach pulses/rev): fan rpm = ( f 60)/( count n 1.5) for an 8-pole fan (4 tach pulses/rev): fan rpm = ( f 60)/( count n 2) if in doubt as to the number of poles the fans used have, or the number of tach output pulses/rev, consult the fan manufacturer? data sheet, or contact the fan vendor fo r more information. fan drive using pwm control the external circuitry required to drive a fan using pwm con- trol is extremely simple. a single nmos fet is the only drive transistor required. the specifications of the mosfet depend on the maximum current required by the fan being driven. typi- cal notebook fans draw a nominal 170 ma, and so sot devices can be used where board space is a constraint. if driving several fans in parallel from a single pwm output, or driving larger server fans, the mosfet will need to handle the higher current requirements. the only other stipulation is that the mosfet should have a gate voltage drive, v gs < 3.3 v, for direct inter- facing to the pwm_out pin. the mosfet should also have a low on-resistance to ensure that there is not signifi cant volt- age drop across the fet. this would reduce the m aximum operating speed of the fan. fi gure 18 shows how a 3-wire fan may be driven using p wm control. +v q1 ndt3055l pwm_out 5v or 12v fan tach/ain adm1030 3.3v 10k typical tach 10k typical 3.3v figure 18. interfacing the adm1030 to a 3-wire fan the ndt3055l n-type mosfet was chosen since it has 3.3 v ga te drive, low on-resistance, and can handle 3.5 a of current. other mosfets may be substituted based on the system? fan drive requirements. +v q1 ndt3055l pwm_out 5v or 12v fan tach/ain adm1030 3.3v 10k typical tach r sense (2 typical) 0.01 f figure 19. interfacing the adm1030 to a 2-wire fan figure 19 shows how a 2-wire fan may be connected to the adm1030. this circuit allows the speed of the 2-wire fan to be measured even though the fan has no dedicated tach sig- nal. a series r sense resistor in the fan circuit converts the fan co mmu tation pulses into a voltage. this is ac-coupled into the adm 103 0 through the 0.01 m f capacitor. on-chip signal conditioning allows accurate monitoring of fan speed. for typical notebook fans drawing approximately 170 ma, a 2 w r sense value is suitable. for fans such as desktop or server fans, that draw more current, r sense may be reduced. the smaller r sense is the better, since more voltage will be developed across the fan, and the fan will spin faster. figure 20 shows a typical plot of the sensing waveform at the tach/ain pin. the most i mpor tant thing is that the negative-going spikes are more than 250 mv in amplitude. this will be the case for most fans when r sense = 2 w . the value of r sense can be reduced as long as the voltage spikes at the tach/ain pin are greater than 250 mv. this allows fan speed to be reliably determined.
rev. a adm1030 ?1 ch1 100mv ch3 50.0mv ch2 5.00mv ch4 50.0mv m 4.00ms a ch1 ?.00mv ch1 1 4 t t tek prevu d: 250mv @: ?58mv figure 20. fan speed sensing waveform at tach/ain pin fan speed measurement the fan counter does not count the fan tach output pulses directly, because the fan speed may be less than 1000 rpm and it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolu- tion is measured by gating an on-chip 11.25 khz oscillator into the input of an 8-bit counter. t he fan speed m easuring circuit is initialized on the rising edge of a pwm high output if fan speed measurement is enabled (bit 2 of configuration r egister 2 = 1). it then starts counting on the rising edge of the second tach pulse and counts for two fan tach periods, until the rising edge of the fourth tach pulse, or until the counter overranges if the fan tach period is too long. the measurement cycle will repeat until monitoring is disabled. the fan speed measurement is stored in the fan speed reading register at address 0x08. the fan speed count is given by: count = ( f 60)/ r n where: f = 11.25 khz r =f an speed in rpm. n = speed range (either 1, 2, 4, or 8) the frequency of the oscillator can be adjusted to suit the expected running speed of the fan by varying n, the speed range. the oscillator frequency is set by bits 7 and 6 of f an c harac teristics register 1 (20h) as shown in table xi. figure 21 shows how the fan measurements relate to the pwm_out pulse trains. table xi. oscillator frequencies oscillator bit 7 bit 6 n frequency (khz) 0 0 1 11.25 0 1 2 5.625 1 0 4 2.812 1 1 8 1.406 clock config 2 reg. bit 2 fan input fan measurement period start of monitoring cycle figure 21. fan speed measurement in situations where different output drive circuits are used for fan drive, it may be desirable to invert the pwm drive signal. setting bit 3 of configuration register 1 (0x00) to 1, inverts the pwm_out signal. this makes the pwm_out pin high for 100% duty cycle. bit 3 of configuration register 1 should gen- erally be set to 1, when using an n-mos device to drive the fan. if using a p-mos device, bit 3 of configuration register 1 should be cleared to 0. fan faults the fan_fault output (pin 8) is an active-low, open-drain output used to signal fan failure to the system p rocessor. writ ing a logic 1 to bit 4 of configuration register 1 (0x00) enables the fan_fault output pin. the fan_fault output is enabled by default. the fan_fault output asserts low only when five consecutive interrupts are generated by the adm1030 device due to the fan running underspeed, or if the fan is completely stalled. note that the fan tach high limit must be exceeded by at least one before a fan_fault can be generated. for example, if we are only interested in getting a fan_fault if the fan stalls, then the fan speed value will be 0xff for a failed f an. therefore, we should make the fan tach high limit = 0xfe to allow fan_fault to be asserted after five consecu- tive fan tach failures. figure 22 shows the relationship between int , fan_fault , and the pwm drive channel. the pwm_out channel is driv- ing a fan at some pwm duty cycle, say 50%, and the fan? tach signal (or fan current for a 2-wire fan) is being monitored at the tach/ain pin. tach pulses are being generated by the fan, during the high time of the pwm duty cycle train. the tach is pulled high during the off time of the pwm train because the fan is connected high-side to the n-mos device. suppose the fan has already failed its fan speed measurement twice previously. looking at figure 22, pwm_out is brought high for two seconds, to restart the fan if it has stalled. some- time later a third tach failure occurs. this is evident by the tach signal being low during the high time of the pwm pulse, causing the fan speed reading register to reach its maximum count of 255. since the tach limit has been exceeded, an interrupt is generated on the int pin. the fan fault bit (bit 1) of inter- r upt status register 1 (register 0x02) will also be asserted. once the processor has acknowledged the int by reading the status register, the int is cleared. pwm_out is then brought high for another 2 seconds to restart the fan. subsequent fan failures cause int to be reasserted and the pwm_out signal is brought high for 2 seconds (fan spin-up default) each time to restart the fan. once the fifth tach failure occurs, the failure is deemed to be catastrophic, and the fan_fault pin is as serted low. pwm_out is brought high to attempt to restart the fan.
rev. a adm1030 ?2 the int pin will continue to generate interrupts after the asser- tion of fan_fault since tach measurement continues even a fter fan failure. should the fan recover from its failure condi- tion, the fan_fault signal will be negated, and the fan will return to its normal operating speed. figure 23 shows a typical application circuit for the adm1030. temperature monitoring can be based around a cpu diode or discrete transistor measuring thermal hotspots. either 2- or 3- wire fans may be monitored by the adm1030, as shown. pwm_out tach/ain int fan_fault status reg read to clear interrupt full speed 2 secs 2 secs 2 secs 3rd tach failure 4th tach failure 5th tach failure continuing tach failure figure 22. operation of fan_fault and interrupt pins sda scl gnd v cc 1 2 3 4 16 15 14 13 adm1030 5 12 6 7 8 9 10 11 int ( smbalert ) tach1/ain1 d+ d- add therm fan_fault nc nc fan_fault to signal fan failure condition 10k cpu interrupt sda scl 2n3904 or pentium iii cpu thermal diode therm signal to throttle cpu clock 3.3v 3.3v 5v tach fan1 3-wire fan pwm_out1 nc nc ndt3055l 10k 3.3v 10k typ. 3.3v 3.3v 10k typ. 2.2k typ. 3.3v 2.2k typ. 3.3v 10k typ. 3.3v nc = no connect figure 23. typical application circuit
rev. a adm1030 ?3 table xii. registers address a7?0 register name in hex comments value registers 0x06?x1a see table xiii. device id register 0x3d this location contains the device identification number. since this device is the adm1030, this register contains 0x30. this register is read only. company id 0x3e this location contains the company identification number (0x41). this register is read only. therm behavior/revision 0x3f this location contains the revision number of the device. the lower four bits reflect device revisions [3:0]. bit 7 of this register is the therm -to-fan enable bit. see table xxiv. configuration register 1 0x00 see table xiv. power-on value = 1001 0000. configuration register 2 0x01 see table xv. power-on value = 0111 1111. status register 1 0x02 see table xvi. power-on value = 0000 0000. status register 2 0x03 see table xvii. power-on value = 0000 0000. manufacturer? test register 0x07 this register is used by the manufacturer for test purposes only. this register should not be read from or written to in normal operation. fan characteristics register 1 0x20 see table xix. power-on value = 0101 1101. fan speed configuration register 0x22 see table xx. power-on value = 0101 0101. fan filter register 0x23 see table xxi. power-on value = 0101 0101. local temperature t min /t range 0x24 see table xxii. power-on value = 0100 0001. remote temperature t min /t range 0x25 see table xxiii. power-on value = 0110 0001. table xiii. value and limit registers address read/write description 0x06 read/only extended temperature resolution (see table xviii). 0x08 read/write fan speed reading?his register contains the fan speed tach measurement. 0x0a read/only local temperature value?his register contains the 8 msbs of the local temperature measurement. 0x0b read/only remote temperature value?his register contains the 8 msbs of the remote temperature reading. 0x0d read/write local temperature offset?ee table xxv. 0x0e read/write remote temperature offset?ee table xxvi. 0x10 read/write fan tach high limit?his register contains the limit for the fan tach measurement. since the tach circuit counts between pulses, a slow fan will result in a large measured value, so exceeding the limit by one is the way to detect a slow or stalled fan. (power-on default = ffh) 0x14 read/write local temperature high limit (power-on default 60 c). 0x15 read/write local temperature low limit (power-on default 0 c). 0x16 read/write local temperature therm limit (power-on default 70 c). 0x18 read/write remote temperature high limit (power-on default 80 c). 0x19 read/write remote temperature low limit (power-on default 0 c). 0x1a read/write remote temperature therm limit (power-on default 100 c).
rev. a adm1030 ?4 table xiv. register 0x00 configuration register 1 power-on default 90h bit name r/ w description 0 monitor read/write setting this bit to a ??enables monitoring of temperature and enables measurement of the fan tach signals. (power-up default = 0.) 1 int enable read/write setting this bit to a ??enables the int output. 1 = enabled 0 = disabled (power-up default = 0). 2 tach/ain read/write clearing this bit to ??selects digital fan speed measurement via the tach pins. setting this bit to ??configures the tach pins as analog inputs that can measure the speed of 2-wire fans via a sense resistor. (power-up default = 0.) 3 pwm invert read/write setting this bit to ??inverts the pwm signal on the output pin. (power-up default = 0 ). the power-up default makes the pwm_out pin go low for 100% duty cycle (suitable for driving the fan using a pmos device). setting this bit to ??makes the pwm_out pin high for 100% duty cycle (intended for driving the fan using an nmos device). 4f an fault enable read/write logic 1 enables fan_fault pin; logic 0 disables fan_fault output. (power-up default = 1.) 6? pwm mode read/write these two bits control the behavior of the fan in auto fan speed control mode. 00 = remote temp controls fan. (program pwm duty cycle in software mode.) 11 = fastest calculated speed controls fan. (program rpm speed in softw are mode.) 7a uto/sw ctrl read/write logic 1 selects automatic fan speed control; logic 0 selects sw control. (power-up default = 1) when under software control, pwm duty cycle or rpm values may be programmed for the fan. table xv. register 0x01 configuration 2 power-on default = 7fh bit name r/ w description 0 pwm 1 en read/write enables fan pwm output when this bit is a ?. 1 unused read/write unused. 2 tach 1 en read/write enables tach input when set to ?. 3 unused 4l oc temp en read/write enables interrupts on local channel when set to ?. 5r emote temp en read/write enables interrupts on remote channel when set to ?.?default is normally enabled, except when a diode fault is detected on power-up. 6 unused read/write unused. 7s w reset read/write when set to ?,?resets the device. self-clears. power-up default = 0.
rev. a adm1030 ?5 table xvi. register 0x02 status register 1 power-on default = 00h bit name r/ w description 0a larm speed read only this bit is set to ??when fan is running at alarm speed. once read, this bit will not reassert on next monitoring cycle, even if the fan is still running at alarm speed. this gives an indication as to when the fan is running full-speed, such as in a therm condition. 1 fan fault read only this bit is set to ??if fan becomes stuck or is running under speed. once r ead, this bit will reassert on next monitoring cycle, if the fan failure condi- tion persists. 2r emote temp high read only ??indicates remote high temperature limit has been exceeded. if the tem- perature is still outside the remote temp high limit, this bit will reassert on next monitoring cycle. 3r emote temp low read only ??indicates remote low temperature limit exceeded (below). if the tempera- ture is still outside the remote temp low limit, this bit will reassert on next monitoring cycle. 4r emote temp therm read only ??indicates remote temperature therm limit has been exceeded. this bit is cleared on a read of status register 1. once cleared, this bit will not get reas- serted even if the therm condition persists. 5r emote diode error read only this bit is set to ??if a short or open is detected on the remote temperature channel. this test is only done on power-up, and if set to 1 cannot be cleared by reading the status register 1. 6l oc temp high read only ??indicates local temp high limit has been exceeded. if the temperature is still outside the local temp high limit, this bit will reassert on next monitoring cycle. 7l oc temp low read only ??indicates local temp low limit has been exceeded (below). if the tem- perature is still outside the local temp low limit, this bit will reassert on next monitoring cycle. table xvii. register 0x03 status register 2 power-up default = 00h bit name r/ w description 0 unused read only unused. 1 unused read only unused. 2 unused read only unused. 3 unused read only unused. 4 unused read only unused. 5 unused read only unused. 6l oc therm read only ??indicates local temperature therm limit has been exceeded. this bit clears on a read of status register 2. once cleared, this bit will not be reasserted even if the therm con- dition persists. 7 therm read only set to ??when therm is pulled low as an input. this bit clears on a read of status register 2. the fan also runs full-speed. table xviii. register 0x06 extended temperature resolution power-on default = 00h bit name r/ w description <2:0> remote temp read only holds extended tem perature resolution bits for remote tem perature channel. <5:3> reserved read only reserved. <7:6> local temp read only holds extended temperature resolution bits for local temperature channel.
rev. a adm1030 ?6 table xix. register 0x20 fan characteristics register 1 power-on default = 5dh bit name r/ w description <2:0> fan 1 spin-up read/write these bits contain the fan spin-up time to allow the fan to overcome its own inertia. 000 = 200 ms 001 = 400 ms 010 = 600 ms 011 = 800 ms 100 = 1 sec 101 = 2 secs (default) 110 = 4 secs 111 = 8 secs <5:3> pwm 1 frequency read/write these bits allow programmability of the nominal pwm output frequency driving the fan. (default = 31 hz.) 000 = 11.7 hz 001 = 15.6 hz 010 = 23.4 hz 011 = 31.25 hz (default) 100 = 37.5 hz 101 = 46.9 hz 110 = 62.5 hz 111 = 93.5 hz <7:6> speed range read/write these bits contain the speed range, n. 00 = 1 (fail speed = 2647 rpm) 01 = 2 (fail speed = 1324 rpm) 10 = 4 (fail speed = 662 rpm) 11 = 8 (fail speed = 331 rpm) table xx. register 0x22 fan speed config register power-on default = 05h bit name r/ w description <3:0> normal/min spd 1 read/write this nibble contains the normal speed value for the fan. when in automatic fan speed control mode, this nibble contains the minimum speed at which the fan will run. default is 0x05 for 33% pwm duty cycle. (see table vii.) <7:4> unused unused. table xxi. register 0x23 fan filter register power-on default = 50h bit name r/ w description <7> spin-up disable read/write when set to 1, disables fan spin-up. <6:5> ramp rate read/write these bits set the ramp rate for the pwm output. 00 = 1 01 = 2 10 = 4 11 = 8 <4:2> adc sample rate read/write these bits set the sampling rate for the adc. 000 = 87.5 hz 0.0625 updates/sec 001 = 175 hz 0.125 updates/sec 010 = 350 hz 0.25 updates/sec 011 = 700 hz 0.5 updates/sec 100 = 1.4 khz (default) 1 update/sec 101 = 2.8 khz 2 updates/sec 110 = 5.6 khz 4 updates/sec 111 = 11.2 khz 8 updates/sec <1> unused read/write unused. <0> fan filter en read/write setting this bit to 1 enables filtering of the pwm_out signal.
rev. a adm1030 ?7 table xxii. register 0x24 local temp t min /t range power-on default = 41h bit name r/ w description <7:3> local temp t min read/write contains the minimum temperature value for automatic fan speed control based on local temperature readings. t min can be programmed to positive values only in 4 c increments. default is 32 c. 00000 = 0 c 00001 = 4 c 00010 = 8 c 00011 = 12 c | | 01000 = 32 c (default) | | | 11110 = 120 c 11111 = 124 c <2:0> local temp t range read/write this nibble contains the temperature range value for automatic fan speed control based on the local temperature readings. 000 = 5 c 001 = 10 c (default) 010 = 20 c 011 = 40 c 100 = 80 c table xxiii. register 0x25 remote temp t min /t range power-on default = 61h bit name r/ w description <7:3> remote temp t min read/write contains the minimum temperature value for automatic fan speed control based on remote temperature readings. t min can be programmed to posi- tive values only in 4 c increments. default is 48 c. 00000 = 0 c 00001 = 4 c 00010 = 8 c 00011 = 12 c | | 01100 = 48 c (default) | | 11110 = 120 c 11111 = 124 c <2:0> remote temp t range read/write this nibble contains the temperature range value for automatic fan speed control based on the remote 1 temperature readings. 000 = 5 c 001 = 10 c (default) 010 = 20 c 011 = 40 c 100 = 80 c
rev. a ?8 c02401??/03(a) adm1030 table xxiv. register 0x3f therm behavior/revision power-on default = 80h bit name r/ w description <7> therm-to-fan enable read/write setting this bit to 1, enables the fan to run full-speed when therm is asserted low. this allows the system to be run in performance mode. clearing this bit to 0 disables the fan from running full-speed whenever therm is asserted low. this allows the system to run in silent mode. (power-on default = 1.) note that this bit has no effect whenever therm is pulled low as an input. <6:4> unused read only unused. read back zeros. <3:0> revision read only this nibble contains the revision number for the adm1030. table xxv. register 0x0d local temp offset power-on default = 00h bit name r/ w description <7> sign read/write when this bit is 0, the local offset will be added to the local temperature reading. when this bit is set to 1, the local temperature offset will be subtracted from the local temperature reading. <6:4> reserved read/write unused. normally read back zeros. <3:0> local offset read/write these four bits are used to add a two? complement offset to the local temperature reading, allowing 15 c to be added to or subtracted from the temperature reading. table xxvi. register 0x0e remote temp offset power-on default = 00h bit name r/ w description <7> sign read/write when this bit is 0, the remote offset will be added to the remote temperature reading. when this bit is set to 1, the remote temperature offset will be subtracted from the remote temperature reading. <6:4> reserved read/write unused. normally read back zeros. <3:0> remote offset read/write these four bits are used to add a two? complement offset to the remote temperature reading, allowing 15 c to be added to or subtracted from the temperature reading. outline dimensions 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches 16 9 8 1 pin 1 seating plane 0.010 0.004 0.012 0.008 0.025 bsc 0.010 0.006 0.050 0.016 8 0 coplanarity 0.004 0.065 0.049 0.069 0.053 0.154 bsc 0.236 bsc compliant to jedec standards mo-137ab 0.193 bsc revision history location page 4/03?ata sheet changed from rev. 0 to rev. a. added esd caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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